ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 1005

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.7.12
Name:
Address:
Access:
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the cor-
responding ADC_CDRx registers.
1 = Corresponding analog channel is enabled and conversion is complete.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last read of ADC_ISR.
1 = At least one General Overrun Error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Error
0 = No Comparison Error since the last read of ADC_ISR.
1 = At least one Comparison Error has occurred since the last read of ADC_ISR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.
• RXBUFF: RX Buffer Full
0 = ADC_RCR or ADC_RNCR have a value other than 0.
1 = Both ADC_RCR and ADC_RNCR have a value of 0.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
EOC15
EOC7
31
23
15
–
–
7
ADC Interrupt Status Register
EOC14
EOC6
30
22
14
ADC_ISR
0x40038030
Read-only
–
–
6
EOC13
EOC5
29
21
13
–
–
5
RXBUFF
EOC12
EOC4
28
20
12
–
4
ENDRX
EOC11
EOC3
27
19
11
–
3
COMPE
EOC10
EOC2
26
18
10
–
2
SAM3S Preliminary
SAM3S Preliminary
GOVRE
EOC9
EOC1
25
17
–
9
1
DRDY
EOC8
EOC0
24
16
–
8
0
1005
1005