ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 454

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.16.10 PMC Clock Generator PLLB Register
Name:
Address:
Access:
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in
• DIVB: Divider
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles x8 before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0 = The PLLB is deactivated.
1 up to 2047 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
454
DIVB
0
1
2 - 255
31
23
15
–
–
7
SAM3S Preliminary
CKGR_PLLBR
0x400E042C
Read-write
30
22
14
–
–
6
29
21
13
–
5
Divider Selected
Divider output is 0
Divider is bypassed (DIVB=1)
Divider output is DIVB
28
20
12
–
4
MULB
DIVB
“PMC Write Protect Mode Register” on page
27
19
11
–
3
PLLBCOUNT
26
18
10
2
MULB
25
17
9
1
6500C–ATARM–8-Feb-11
466.
24
16
8
0