ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 294

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 18-3. Code Read Optimization for FWS = 3
Note:
18.3.2.3
Figure 18-4. Data Read Optimization for FWS = 1
294
Buffer (128bits)
Buffer 1 (128bits)
Buffer 0 (128bits)
ARM Request
Data To ARM
Flash Access
Master Clock
ARM Request
Data To ARM
Flash Access
Master Clock
When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
(32-bit)
SAM3S Preliminary
(32-bit)
Data Read Optimization
@Byte 0
XXX
@Byte 0
XXX
XXX
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit)
prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system
performance. This buffer is added in order to store the requested data plus all the data contained
in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is
equal to 1 (see
Note:
Bytes 0-15
XXX
XXX
Bytes 0-15
Bytes 0-3
@ 4
No consecutive data read accesses are mandatory to benefit from this optimization.
XXX
@ 8
4-7
Figure
@4
0-3
18-4).
@ 12
@8
8-11
4-7
Bytes 0-15
@12 @16
Bytes 16-31
8-11
12-15
@ 16
12-15
Bytes 0-15
@20
Bytes 16-31
16-19 20-23
@24
@ 20
16-19
@28 @32
Bytes 32-47
24-27
@ 24
20-23
28-31 32-35
24-27
@ 28
@36 @40
Bytes 16-31
Bytes 16-31
36-39
28-31
@ 32
@44 @48 @52
Bytes 48-63
Bytes 32-47
40-43
6500C–ATARM–8-Feb-11
Bytes 32-47
44-47
@ 36
32-35
48-51