ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 215

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11. Debug and Test Features
11.1
11.2
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The SAM3 Series Microcontrollers feature a number of complementary debug and test
capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port
(SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as
downloading code and single-stepping through programs. It also embeds a serial wire trace.
Figure 11-1. Debug and Test Block Diagram
• Debug access to all memory and registers in the system, including Cortex-M3 register bank
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• IEEE1149.1 JTAG Boundary-can on All Digital Pins
when the core is running, halted, or held in reset.
system profiling
Boundary
TAP
SWJ-DP
Reset
Test
and
SAM3S Preliminary
POR
JTAGSEL
TDO/TRACESWO
TMS
TCK/SWCLK
TDI
TST
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