ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 491

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 28-7. Event Detector on Input Lines (Figure represents line 0)
28.5.10.1
28.5.10.2
28.5.10.3
28.5.10.4
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Resynchronized input on line 0
Example
Interrupt Mode Configuration
Edge or Level Detection Configuration
Falling/Rising Edge or Low/High Level Detection Configuration.
If generating an interrupt is required on the following:
The configuration required is described below.
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in
PIO_AIMER.
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously con-
figured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in Edge detection by writing
32’h0000_00C7 in PIO_ESR.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing
32’h0000_00B5 in PIO_REHLSR.
• Rising edge on PIO line 0
• Falling edge on PIO line 1
• Rising edge on PIO line 2
• Low Level on PIO line 3
• High Level on PIO line 4
• High Level on PIO line 5
• Falling edge on PIO line 6
• Rising edge on PIO line 7
• Any edge on the other lines
PIO_REHLSR[0]
PIO_FELLSR[0]
Rising Edge
Falling Edge
Detector
High Level
Low Level
Detector
Detector
Detector
Detector
Edge
PIO_FRLHSR[0]
0
0
1
1
PIO_LSR[0]
PIO_ESR[0]
PIO_ELSR[0]
1
0
PIO_AIMER[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
SAM3S Preliminary
SAM3S Preliminary
1
0
Event detection on line 0
Event Detector
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