ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 421

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25. Clock Generator
25.1
25.2
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The Clock Generator User Interface is embedded within the Power Management Controller and
is described in
the Clock Generator registers are named CKGR_.
The Clock Generator is made up of:
It provides the following clocks:
PLLBCK is the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
• A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
• A Low Power RC Oscillator
• A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator which can be bypassed
• A factory programmed Fast RC Oscillator, 3 output frequencies can be selected: 4, 8 or
• Two 60 to 130 MHz programmable PLL (input from 3.5 to 20 MHz), capable of providing the
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic
• PLLACK is the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
12 MHz. By default 4 MHz is selected.
clock MCK to the processor and to the peripherals.
Resonator-based Oscillator or 4/8/12 MHz Fast RC Oscillator
Section 26.16 ”Power Management Controller (PMC) User
SAM3S Preliminary
Interface”. However,
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