ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 374
![IC MCU 32BIT 256KB FLASH 100BGA](/photos/12/32/123223/100-lfbga_sml.jpg)
ATSAM3S4CA-CU
Manufacturer Part Number
ATSAM3S4CA-CU
Description
IC MCU 32BIT 256KB FLASH 100BGA
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Package
100LFBGA
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
79
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S4CA-CU
Manufacturer:
SANYO
Quantity:
1 000
- Current page: 374 of 1118
- Download datasheet (24Mb)
23.8.4
23.8.4.1
23.8.4.2
374
SAM3S Preliminary
Write Mode
Write is Controlled by NWE (WRITE_MODE = 1):
Write is Controlled by NCS (WRITE_MODE = 0)
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi-
cates which signal controls the write operation.
Figure 23-11
put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are
turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the
programmed waveform on NCS.
Figure 23-11. WRITE_MODE = 1. The write operation is controlled by NWE
Figure 23-12
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
Figure 23-12. WRITE_MODE = 0. The write operation is controlled by NCS
A [23:0]
A [23:0]
D[7:0]
D[7:0]
NWE
NWE
MCK
MCK
NCS
NCS
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
6500C–ATARM–8-Feb-11
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