ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 220
![IC MCU 32BIT 256KB FLASH 100BGA](/photos/12/32/123223/100-lfbga_sml.jpg)
ATSAM3S4CA-CU
Manufacturer Part Number
ATSAM3S4CA-CU
Description
IC MCU 32BIT 256KB FLASH 100BGA
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-CU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Package
100LFBGA
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
79
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S4CA-CU
Manufacturer:
SANYO
Quantity:
1 000
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11.5.6
11.5.6.1
220
SAM3S Preliminary
ITM (Instrumentation Trace Macrocell)
How to Configure the ITM
The DWT contains counters for the items that follow:
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
The following example describes how to output trace data in asynchronous trace mode.
• Watchpoint event to halt core
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
• Software trace: Software can write directly to ITM stimulus registers. This can be done
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
• Configure the TPIU for asynchronous trace mode (refer to
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
• Write 0x00010015 into the Trace Control Register:
• Write 0x1 into the Trace Enable Register:
• Write 0x1 into the Trace Privilege Register:
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
thanks to the “printf” function. For more information, refer to
Configure the
counter to generate the timestamp.
Configure the
Lock Access Register (Address: 0xE0000FB0)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
– Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
– Fix the ATB ID to 1
– Enable the Stimulus port 0
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
ITM”.
TPIU”)
Section 11.5.6.3 “5.4.3. How to
Section 11.5.6.1 “How to
6500C–ATARM–8-Feb-11
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