ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 766

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

34.6.14.5
34.6.15
766
SAM3S Preliminary
2-bit Gray Up/Down Counter for Stepper Motor
Speed Measurement
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on
the TC_CV0 register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form
a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in
timer/counter channels 0 and 1. The direction status is reported on TC_QISR register.
When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2
must be configured in waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit
field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC
value. ACPC field must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are
set.
Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). ABETRG bit field of
TC_CMR0 must be configured at 1 to get TIOA as a trigger for this channel.
EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and LDRA
field must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared
(LDRB must be set to 0x01). As a consequence, at the end of each time base period the differ-
entiation required for the speed calculation is performed.
The process must be started by configuring the TC_CR register with CLKEN and SWTRG.
The speed can be read on TC_RA0 register in TC_CMR0.
Channel 1 can still be used to count the number of revolutions of the motor.
Each channel can be independently configured to generate a 2-bit gray count waveform on cor-
responding TIOA,TIOB outputs by means of GCEN bit in TC_SMMRx registers.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx registers.
It is mandatory to configure the channel in WAVE mode in TC_CMR register.
The period of the counters can be programmed on TC_RCx registers.
6500C–ATARM–8-Feb-11