ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 995

IC MCU 32BIT 256KB FLASH 100BGA

ATSAM3S4CA-CU

Manufacturer Part Number
ATSAM3S4CA-CU
Description
IC MCU 32BIT 256KB FLASH 100BGA
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S4CA-CU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Package
100LFBGA
Device Core
ARM Cortex M3
Family Name
AT91
Maximum Speed
64 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
79
Interface Type
I2C/I2S/SPI/UART/USART/USB
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Number Of Timers
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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• SETTLING: Analog Settling Time
• ANACH: Analog Change
• TRACKTIM: Tracking Time
• TRANSFER: Transfer Period
• USEQ: Use Sequence Enable
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Value
Tracking Time = (TRACKTIM + 1) * ADCClock periods.
Transfer Period = (TRANSFER * 2 + 3) ADCClock periods.
Value
Value
0
1
2
3
0
1
0
1
NUM_ORDER
REG_ORDER
ALLOWED
AST17
Name
AST3
AST5
AST9
NONE
Name
Name
Description
3 periods of ADCClock
5 periods of ADCClock
9 periods of ADCClock
17 periods of ADCClock
Description
Normal Mode: The controller converts channels in a simple numeric order.
User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2
registers.
Description
No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers
SAM3S Preliminary
SAM3S Preliminary
995
995

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