AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 189

• Manufacturer Part Number: AT90CAN128-15AZ
• Description: MCU AVR 128K FLASH 15MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-15AZ

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 53
• Eeprom Size: 4K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: CAN, I²C, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.8.3
17.8.4
17.8.5
7679H–CAN–08/08
Receive Complete Flag and Interrupt
Receiver Error Flags
Parity Checker
The USARTn Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXCn) flag indicates if there are unread data present in the receive
buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),
the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USARTn
Receive Complete interrupt will be executed as long as the RXCn flag is set (provided that glo-
bal interrupts are enabled). When interrupt-driven data reception is used, the receive complete
routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new
interrupt will occur once the interrupt routine terminates.
The USARTn Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and
Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is
that they are located in the receive buffer together with the frame for which they indicate the
error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive
buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another
equality for the error flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upward compat-
ibility of future USART implementations. None of the error flags can generate interrupts.
The Frame Error (FEn) flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one),
and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag
is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except
for the first, stop bits. For compatibility with future devices, always set this bit to zero when writ-
ing to UCSRnA.
The Data OverRun (DORn) flag indicates data loss due to a receiver buffer full condition. A Data
OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in
the Receive Shift Register, and a new start bit is detected. If the DORn flag is set there was one
or more serial frame lost between the frame last read from UDRn, and the next frame read from
UDRn. For compatibility with future devices, always write this bit to zero when writing to UCS-
RnA. The DORn flag is cleared when the frame received was successfully moved from the Shift
Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see
The Parity Checker is active when the high USARTn Parity mode (UPMn1) bit is set. Type of
Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the
Parity Checker calculates the parity of the data bits in incoming frames and compares the result
with the parity bit from the serial frame. The result of the check is stored in the receive buffer
together with the received data and stop bits. The Parity Error (UPEn) flag can then be read by
software to check if the frame had a Parity Error.
“Parity Bit Calculation” on page 182
and
“Parity Checker” on page
AT90CAN32/64/128
189.
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