AT90CAN128-15AZ Atmel, AT90CAN128-15AZ Datasheet - Page 222

MCU AVR 128K FLASH 15MHZ 64TQFP

AT90CAN128-15AZ

Manufacturer Part Number
AT90CAN128-15AZ
Description
MCU AVR 128K FLASH 15MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheets

Specifications of AT90CAN128-15AZ

Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
53
Eeprom Size
4K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
CAN, I²C, SPI, UART/USART
Core Size
8-Bit
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
CAN, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
90C
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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18.8.2
222
AT90CAN32/64/128
Master Receiver Mode
In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see
Figure
mat of the following address packet determines whether Master Transmitter or Master Receiver
mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,
MR mode is entered. All the status codes mentioned in this section assume that the prescaler
bits are zero or are masked to zero.
Figure 18-13. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will
then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the
status code in TWSR will be 0x08 (See
transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-
ing value to TWCR:
When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in
flag is set high by hardware. This scheme is repeated until the last byte has been received. After
the last byte has been received, the MR should inform the ST by sending a NACK after the last
received data byte. The transfer is ended by generating a STOP condition or a repeated START
condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWCR
value
TWCR
value
18-13). In order to enter a Master mode, a START condition must be transmitted. The for-
SDA
SCL
TWINT
TWINT
TWINT
Table
1
1
1
18-12. Received data can be read from the TWDR Register when the TWINT
Device 1
RECEIVER
MASTER
TWEA
TWEA
TWEA
X
X
X
TWSTA
TWSTA
TWSTA
1
0
0
TRANSMITTER
Device 2
SLAVE
Table
TWSTO
TWSTO
TWSTO
0
0
1
18-3). In order to enter MR mode, SLA+R must be
Device 3
TWWC
TWWC
TWWC
X
X
X
........
TWEN
TWEN
TWEN
1
1
1
Device n
0
0
0
R1
TWIE
TWIE
TWIE
7679H–CAN–08/08
X
X
X
V
CC
R2

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