MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 159

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.2
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
5.3
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1
5.3.2
5.3.2.1
Read: See individual bit descriptions
Write: See individual bit descriptions
Freescale Semiconductor
Module Base + 0x0015
Starting address location affected by INITRG register setting.
Reset
W
R
External Signal Description
Memory Map and Register Definition
Address
0x0015
0x0016
0x001F
Offset
Module Memory Map
Register Descriptions
Interrupt Test Control Register
0
0
7
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
= Unimplemented or Reserved
0
0
6
Figure 5-2. Interrupt Test Control Register (ITCR)
MC9S12C-Family / MC9S12GC-Family
0
0
5
Table 5-1. INT Memory Map
WRTINT
Rev 01.24
0
4
Use
ADR3
1
3
Chapter 5 Interrupt (INTV1) Block Description
ADR2
1
2
ADR1
1
1
Access
R/W
R/W
R/W
ADR0
1
0
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