MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 202

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.4
202
Module Base + 0x0024
Starting address location affected by INITRG register setting.
Reset
Field
CNT
TBF
5:0
7
W
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was
last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit
is cleared when ARM in DBGC1 is written to a 1.
Count Value — The CNT bits indicate the number of valid data words stored in the trace buffer.
the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls
over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The
DBGCNT register is cleared when ARM in DBGC1 is written to a 1.
TBF
Debug Count Register (DBGCNT)
0
7
= Unimplemented or Reserved
0
0
6
TBF
0
0
0
0
1
1
Figure 7-8. Debug Count Register (DBGCNT)
Table 7-8. DBGCNT Field Descriptions
MC9S12C-Family / MC9S12GC-Family
Table 7-9. CNT Decoding Table
0
5
000000
000001
000010
111110
111111
000000
000001
111111
CNT
..
..
..
..
Rev 01.24
0
4
64 words valid; if BEGIN = 1, the
oldest data has been overwritten
breakpoint will be generated if
Description
ARM bit will be cleared. A
by most recent data
64 words valid,
62 words valid
63 words valid
DBGBRK = 1
No data valid
2 words valid
Description
1 word valid
0
3
..
..
CNT
0
2
Freescale Semiconductor
0
1
Table 7-9
0
0
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