MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 286

IC MCU 64K FLASH 4K RAM 80-QFP

MC9S12C64CFUE

Manufacturer Part Number
MC9S12C64CFUE
Description
IC MCU 64K FLASH 4K RAM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12C64CFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
60
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
80PQFP
Family Name
HCS12
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|5 V
Height
2.4 mm
Length
14 mm
Supply Voltage (max)
2.75 V, 5.5 V
Supply Voltage (min)
2.35 V, 2.97 V
Width
14 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.6
The interrupts/reset vectors requested by the CRG are listed in
chapter for related vector addresses and priorities.
9.6.1
The CRGV4 generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts
are locally disabled by setting the RTIE bit to 0. The real-time interrupt flag (RTIF) is set to 1 when a
timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from pseudo-stop if the RTI interrupt is enabled.
9.6.2
The CRGV4 generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either
from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the
LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
9.6.3
The CRGV4 generates a self-clock mode interrupt when the SCM condition of the system has changed,
either entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable
bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset
(POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure.
For details on the clock quality check refer to
is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set
to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
286
Interrupts
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode Interrupt
Real-time interrupt
Interrupt Source
LOCK interrupt
SCM interrupt
Table 9-15. CRG Interrupt Vectors
MC9S12C-Family / MC9S12GC-Family
Section 9.4.4, “Clock Quality
Mask
CCR
Rev 01.24
I bit
I bit
I bit
CRGINT (LOCKIE)
CRGINT (SCMIE)
CRGINT (RTIE)
Local Enable
Table
9-15. Refer to the device overview
Checker.” If the clock monitor
Freescale Semiconductor

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