MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 302

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
1. WUPIE and WUPE (see
2. Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the
10.3.2.7
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Read: Anytime
Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
302
Module Base + 0x0006
mechanism from stop or wait is required.
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
OVRIE
RXFIE
Field
1
0
Reset:
W
R
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receiver Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
MSCAN Transmitter Flag Register (CANTFLG)
(CANRFLG)”).
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
7
Table 10-10. CANRIER Register Field Descriptions (continued)
Section 10.3.2.1, “MSCAN Control Register 0
Figure 10-10. MSCAN Transmitter Flag Register (CANTFLG)
= Unimplemented
6
0
0
MC9S12C-Family / MC9S12GC-Family
0
0
5
Rev 01.24
NOTE
4
0
0
Description
(CANCTL0)”) must both be enabled if the recovery
0
0
3
TXE2
Section 10.3.2.5, “MSCAN Receiver
2
1
Freescale Semiconductor
TXE1
1
1
TXE0
0
1