MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 200

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7 Debug Module (DBGV1) Block Description
7.3.2.2
200
Module Base + 0x0021
Starting address location affected by INITRG register setting.
Reset
Field
TRG
CF
3:0
AF
BF
7
6
5
W
R
Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger A did not match
1 Trigger A match
Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger B did not match
1 Trigger B match
Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This
bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Comparator C did not match
1 Comparator C match
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown
Section 7.4.2.5, “Trigger
AF
Debug Status and Control Register (DBGSC)
0
7
= Unimplemented or Reserved
Figure 7-5. Debug Status and Control Register (DBGSC)
BF
0
6
TRG Value
Modes,” for more detail.
Table 7-5. DBGSC Field Descriptions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1111
Table 7-6. Trigger Mode Encoding
MC9S12C-Family / MC9S12GC-Family
↓
CF
0
5
Rev 01.24
0
0
4
A and Not B (full mode)
Description
A then event only B
A and B (full mode)
(Defaults to A only)
Outside range
Event only B
Inside range
Reserved
Meaning
A then B
A only
A or B
0
3
0
2
TRG
Freescale Semiconductor
0
1
Table
7-6. See
0
0