MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 13

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

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D.2.22
D.2.23
D.2.24
D.2.25
D.2.26
D.3
D.3.1
D.3.2
D.3.3
D.3.4
D.4
D.4.1
D.4.2
D.4.3
D.4.4
D.5
D.5.1
D.5.2
D.5.3
D.5.4
D.5.5
D.5.6
D.5.7
D.6
D.6.1
D.6.2
D.6.3
D.6.4
D.6.5
D.6.6
D.6.7
D.6.8
D.6.9
D.6.10
D.6.11
D.6.12
D.6.13
D.6.14
D.6.15
D.6.16
D.7
M68HC16 Z SERIES
USER’S MANUAL
Standby RAM Module ............................................................................ D-23
Masked ROM Module ............................................................................. D-25
Analog-to-Digital Converter Module ....................................................... D-29
Queued Serial Module ............................................................................ D-38
Multichannel Communication Interface Module ..................................... D-54
Master Shift Registers .................................................................... D-22
Test Module Shift Count Register .................................................. D-22
Test Module Repetition Count Register ......................................... D-22
Test Module Control Register ......................................................... D-22
Test Module Distributed Register ................................................... D-22
RAM Module Configuration Register .............................................. D-23
RAM Test Register ......................................................................... D-24
Array Base Address Register High ................................................. D-24
Array Base Address Register Low ................................................. D-24
Masked ROM Module Configuration Register ................................ D-25
ROM Array Base Address Registers .............................................. D-27
ROM Signature Registers High ...................................................... D-27
ROM Bootstrap Words ................................................................... D-28
ADC Module Configuration Register .............................................. D-30
ADC Test Register ......................................................................... D-30
Port ADA Data Register ................................................................. D-30
ADC Control Register 0 .................................................................. D-31
ADC Control Register 1 .................................................................. D-32
ADC Status Register ...................................................................... D-36
Right Justified, Unsigned Result Register ...................................... D-36
QSM Configuration Register .......................................................... D-38
QSM Test Register ......................................................................... D-39
QSM Interrupt Level Register/Interrupt Vector Register ................. D-39
SCI Control Register ...................................................................... D-40
SCI Control Register 1 ................................................................... D-41
SCI Status Register ........................................................................ D-43
SCI Data Register .......................................................................... D-44
Port QS Data Register .................................................................... D-44
Port QS Pin Assignment Register/Data Direction Register ............ D-45
QSPI Control Register 0 ................................................................. D-46
QSPI Control Register 1 ................................................................. D-48
QSPI Control Register 2 ................................................................. D-49
QSPI Control Register 3 ................................................................. D-50
Receive Data RAM ......................................................................... D-51
Transmit Data RAM ........................................................................ D-52
Command RAM .............................................................................. D-52
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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