MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 247

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

10.3.3 SPI Operating Modes
10.3.3.1 Master Mode
M68HC16 Z SERIES
USER’S MANUAL
The SPI operates in either master or slave mode. Master mode is used when the MCU
originates data transfers. Slave mode is used when an external device initiates serial
transfers to the MCU. The MSTR bit in SPCR selects master or slave operation.
Setting the MSTR bit in SPCR selects master mode operation. In master mode, the
SPI can initiate serial transfers but cannot respond to externally initiated transfers.
When the slave-select input of a device configured for master mode is asserted, a
mode fault occurs.
When using the SPI in master mode, include the following steps:
When the SPI reaches the end of the transmission, it sets the SPIF flag in the SPSR.
If the SPIE bit in the SPCR is set, an interrupt request is generated when SPIF is as-
serted. After the SPSR is read with SPIF set, and then the SPDR is read or written to,
the SPIF flag is automatically cleared.
Master in, slave out (MISO)
Master out, slave in (MOSI)
1. Write to the MMCR, MIVR, and ILSPI. Refer to
2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and
3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK (serial
4. Write to the SPCR to assign values for BAUD, CPHA, CPOL, SIZE, LSBF,
5. Enable the slave device.
6. Write appropriate data to the SPI data register to initiate the transfer.
Serial clock (SCK)
Slave select (SS)
more information.
(optionally) SS. MISO is used for serial data input in master mode, and MOSI
is used for serial data output. Either or both may be necessary, depending on
the particular application. SS is used to generate a mode fault in master mode.
If this SPI is the only possible master in the system, the SS pin may be used for
general-purpose I/O.
clock) and MOSI pins as outputs. Configure MISO and (optionally) SS as in-
puts.
WOMP, and SPIE. Set the MSTR bit to select master operation. Set the SPE
bit to enable the SPI.
Pin Name
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 10-3 SPI Pin Functions
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Go to: www.freescale.com
Provides serial data input to the SPI
Provides serial data output from the SPI
Provides serial output from the SPI
Provides serial input to the SPI
Provides clock output from the SPI
Provides clock input to the SPI
Detects bus-master mode fault
Selects the SPI for an externally-initiated serial transfer
Function
10.5 MCCI Initialization
10-7
for