MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 303

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

M68HC16 Z SERIES
USER’S MANUAL
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
4A, 5A Rise and Fall Time (All outputs except CLKOUT)
4B, 5B External Clock Input Rise and Fall Time
Num
2, 3
4, 5
14A
14B
27A
29A
F1
1A
1B
9A
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
6
7
8
9
1
Frequency of Operation
Clock Period
ECLK Period
External Clock Input Period
Clock Pulse Width
CLKOUT Rise and Fall Time
Clock High to ADDR, FC, SIZ Valid
Clock High to ADDR, Data, FC, SIZ High Impedance
Clock High to ADDR, FC, SIZ Invalid
Clock Low to AS, DS, CS Asserted
AS to DS or CS Asserted (Read)
ADDR, FC, SIZ Valid to AS, CS, (and DS Read) Asserted
Clock Low to AS, DS, CS Negated
AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold)
AS, CS (and DS Read) Width Asserted
DS, CS Width Asserted (Write)
AS, CS (and DS Read) Width Asserted (Fast Cycle)
AS, DS, CS Width Negated
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W High
Clock High to R/W High
Clock High to R/W Low
R/W High to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle)
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
DS, CS Negated to Data In High Impedance
(V
Table A-15 Low Voltage 16.78-MHz AC Timing
DD
3
and V
Freescale Semiconductor, Inc.
For More Information On This Product,
DDSYN
2
6
Characteristic
ELECTRICAL CHARACTERISTICS
5
= 2.7 to 3.6Vdc, V
Go to: www.freescale.com
4
4
2
3
4
7, 8
7
SS
= 0 Vdc, T
A
= T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DVASN
t
t
CHAZx
CHAZn
t
t
SWAW
SWDW
t
t
SNDOI
BELCL
t
t
t
t
t
CHRH
CHDO
t
t
CHAV
CHSZ
SNRN
CHRL
RAAA
RASA
DVSA
SNDN
XCHL
CLSA
STSA
AVSA
CLSN
t
ECW
SNAI
SNDI
SHDI
t
Ecyc
Xcyc
SWA
DICL
L
t
XCrf
t
CW
cyc
Crf
t
SN
f
rf
to T
H
)
1
59.6
Min
476
236
–15
110
64
24
32
15
15
45
40
40
15
15
70
15
15
15
20
—
—
—
—
0
0
0
2
0
2
2
0
0
0
5
0
0
16.78 MHz
Max
35
59
25
15
29
59
30
30
30
80
55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
8
5
Unit
A-19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns