MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 231

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

9.3.5.4 Slave Wrap-Around Mode
9.3.6 Peripheral Chip Selects
9.4 Serial Communication Interface
M68HC16 Z SERIES
USER’S MANUAL
The QSPI transmits as many bits as it receives at each queue address, until the
BITS[3:0] value is reached or SS is negated. SS does not need to go high between
transfers as the QSPI transfers data until reaching the end of the queue, whether SS
remains low or is toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wrap-around mode is enabled.
Slave wrap-around mode is enabled by setting the WREN bit in SPCR2. The queue
can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on
the state of the WRTO bit in SPCR2. Slave wrap-around operation is identical to mas-
ter wrap-around operation.
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in
each command byte. More than one chip-select signal can be asserted at a time, and
more than one external device can be connected to each PCS pin, provided proper
fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates
slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a
mode fault occurs.
To configure a peripheral chip-select, set the appropriate bit in PQSPAR, then config-
ure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value
of the bit in PORTQS that corresponds to the chip-select pin determines the base state
of the chip-select signal. If base state is zero, chip-select assertion must be active high
(PCS bit in command RAM must be set); if base state is one, assertion must be active
low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during re-
set. If no new data is written to PORTQS before pin assignment and configuration as
an output, the base state of chip-select signals is zero and chip-select pins should thus
be driven active-high.
The serial communication interface (SCI) communicates with external devices through
an asynchronous serial bus. The SCI uses a standard non-return to zero (NRZ) trans-
mission format. The SCI is fully compatible with other Freescale SCI systems, such as
those on M68HC11 and M68HC05 devices.
transmitter.
Figure 9-11
Freescale Semiconductor, Inc.
For More Information On This Product,
is a block diagram of the SCI receiver.
QUEUED SERIAL MODULE
Go to: www.freescale.com
Figure 9-10
is a block diagram of the SCI
9-21