MC68HC16Z1CAG25 Freescale Semiconductor, MC68HC16Z1CAG25 Datasheet - Page 397

• Manufacturer Part Number: MC68HC16Z1CAG25
• Description: IC MCU 16BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CAG25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Cpu Family: HC16
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: SCI/SPI/UART
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

D.3 Standby RAM Module
D.3.1 RAM Module Configuration Register
RAMMCR — RAM Module Configuration Register
STOP — Low-Power Stop Mode Enable
RLCK — RAM Base Address Lock
RASP[1:0] — RAM Array Space
M68HC16 Z SERIES
USER’S MANUAL
RESET:
STOP
15
1
Table D-19
This bit controls whether SRAM operates normally or enters low-power stop mode. In
low-power stop mode, the array retains its contents, but cannot be read or written. This
bit can be read or written at any time.
RLCK defaults to zero on reset; it can be written once to a one, and may be read at
any time.
The RASP field limits access to the SRAM array in microcontrollers that support sep-
arate user and supervisor operating modes. RASP1 has no effect because the CPU16
operates in supervisor mode only. This bit may be read or written at any time. Refer to
Table
0 = SRAM operates normally.
1 = SRAM enters low-power stop mode.
0 = SRAM base address registers can be written.
1 = SRAM base address registers are locked and cannot be modified.
0
0
D-20.
NOTES:
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
0
0
shows the SRAM address map.
1
0
0
Table D-20 SRAM Array Address Space Type
Freescale Semiconductor, Inc.
RLCK
15
RASP[1:0]
11
For More Information On This Product,
0
Table D-19 SRAM Address Map
X0
X1
0
0
RAM Array Base Address Register High (RAMBAH)
RAM Array Base Address Register Low (RAMBAL)
RAM Module Configuration Register (RAMMCR)
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REGISTER SUMMARY
9
1
RASP[1:0]
RAM Test Register (RAMTST)
Program and data accesses
8
1
Program access only
Space
NOT USED
0
$YFFB00
D-23
0