R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 134
![MCU 256K FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24268NVFQV
Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
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Section 4 Exception Handling
4.7
Illegal instruction exception handling starts when the CPU executing an illegal instruction code is
detected. Illegal instruction exception handling can be executed at all times in the program
execution state.
The illegal instruction exception handling is as follows:
1. The values in the PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the exception is generated, the
Table 4.5 shows the status of CCR and EXR after execution of illegal instruction exception
handling.
Table 4.5
Legend:
1:
0:
⎯: Retains value prior to execution
Illegal instruction codes will not be searched for in the fields that do not affect instruction
definitions, such as the EA extension or register fields. Instruction codes for an instruction formed
with several words are detected independently, and combined instruction codes are not detected.
Undefined instruction codes must not be executed. The general register contents after execution of
an undefined instruction code or illegal instruction exception handling cannot be guaranteed. The
stack pointer during illegal instruction exception handling and the PC value that will be saved are
also not guaranteed.
Page 104 of 1372
Interrupt Control Mode
0
2
start address of the exception service routine is loaded from the vector table to the PC, and
program execution starts from that address.
Set to 1
Cleared to 0
Illegal Instruction Exception Handling
Status of CCR and EXR after Illegal Instruction Exception Handling
I
1
1
CCR
UI
⎯
⎯
T
⎯
0
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
EXR
I2 to I0
⎯
⎯
Jul 09, 2010
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