R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 503
![MCU 256K FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24268NVFQV
Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R4F24268NVFQV
Manufacturer:
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H8S/2426, H8S/2426R, H8S/2424 Group
(4)
At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low
level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer-
enabled state.
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the
EDREQ pin from the previous end of transfer, etc.
(5)
When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in
EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be
requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request
when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1.
(6)
If the last EXDMAC transfer cycle and a CBR refresh cycle* occur simultaneously, note that
although the CBR refresh* and the last transfer cycle may be executed consecutively, ETEND
may also go low in this case for the refresh cycle*.
Note: * Not supported in the 5-V version.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Activation Source Acceptance
Enabling Interrupt Requests when IRF = 1 in EDMDR
ETEND Pin and CBR Refresh Cycle*
Section 8 EXDMA Controller (EXDMAC)
Page 473 of 1372
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