R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 183

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Name
Chip select 4/
row address strobe 4*
write enable*
Chip select 5/
row address strobe 5*
SDRAMφ*
Chip select 6
Chip select 7
Upper column address
strobe*
upper data mask enable*
Lower column address strobe/
lower data mask enable
Output enable/clock enable
Wait
Bus request
Bus request acknowledge
Bus request output
1
/
2
2
1
1
/
/
2
Symbol
CS4/
RAS4*
WE*
CS5/
RAS5*
SDRAMφ*
CS6
CS7
UCAS*
DQMU*
LCAS*
DQML*
OE*
CKE*
WAIT
BREQ
BACK
BREQO
1
2
/
2
1
1
1
1
/
/
/
2
/
2
2
I/O
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Function
Strobe signal indicating that area 4 is
selected, DRAM row address strobe signal
when area 4 is DRAM space, or write
enable signal of the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 5 is
selected, DRAM row address strobe signal
when area 5 is DRAM space, or dedicated
clock signal for the synchronous DRAM
when the synchronous DRAM interface is
selected.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal, upper data mask
signal of 16-bit synchronous DRAM space,
or data mask signal of 8-bit synchronous
DRAM space.
16-bit DRAM space lower column address
strobe signal or lower data mask signal for
the 16-bit synchronous DRAM space.
Output enable signal for the DRAM space
or clock enable signal for the synchronous
DRAM space.
Wait request signal when accessing
external address space.
Request signal for release of bus to
external bus master.
Acknowledge signal indicating that bus has
been released to external bus master.
External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
Section 6 Bus Controller (BSC)
Page 153 of 1372