R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 498
![MCU 256K FLASH 48K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24268NVFQV
Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R4F24268NVFQV
Manufacturer:
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Section 8 EXDMA Controller (EXDMAC)
8.4.12
The operation for ending DMA transfer depends on the transfer end conditions. When DMA
transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has
ended.
(1)
When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel
and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a
transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set
to 1.
In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
(2)
If an address overflows the repeat area when a repeat area specification has been made and repeat
interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow
interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit
in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
(3)
When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of
the DMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, DMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.
Page 468 of 1372
Transfer End by 1 → 0 Transition of EDTCR
Transfer End by Repeat Area Overflow Interrupt
Transfer End by 0-Write to EDA Bit in EDMDR
Ending DMA Transfer
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
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