R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 212

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.3.11
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Note:
Page 182 of 1372
Bit
15
14
13
12
Group. The DRAM interface is not supported by the 5-V version.
Bit Name
CMF
CMIE
RCW1
RCW0
*
Refresh Control Register (REFCR)
Only 0 can be written, to clear the flag.
0
0
0
0
Initial Value
R/W
R/(W)*
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
•
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF =
1 while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010