R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 316

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
(3)
If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the read cycle.
Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
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Read after Write
Address bus
CS (area A)
CS (area B)
HWR, LWR
Data bus
Figure 6.79 Example of Idle Cycle Operation (Read after Write)
RD
φ
(a) No idle cycle insertion
T
(ICIS2 = 0)
1
Bus cycle A
Long output floating time
T
2
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS2 = 1, initial value)
T
H8S/2426, H8S/2426R, H8S/2424 Group
2
T
3
REJ09B0466-0350 Rev. 3.50
Idle cycle
T
i
Bus cycle B
T
1
T
2
Jul 09, 2010