R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 353

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
7.3.4
DMACR controls the operation of each DMAC channel.
The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in
channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1
(channel 1B). In short address mode, channels A and B operate independently, and in full address
mode, channels A and B operate together. The bit functions in the DMACR registers differ
according to the transfer mode.
(1)
• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
Short Address Mode
Bit Name
DTSZ
DTID
DMA Control Registers (DMACRA and DMACRB)
Initial Value
0
0
R/W
R/W
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Data Transfer Increment/Decrement
Selects incrementing or decrementing of MAR
after every data transfer in sequential mode or
repeat mode. In idle mode, MAR is neither
incremented nor decremented.
0: MAR is incremented after a data transfer
•
•
1: MAR is decremented after a data transfer
•
•
(Initial value)
When DTSZ = 0, MAR is incremented by 1
When DTSZ = 1, MAR is incremented by 2
When DTSZ = 0, MAR is decremented by 1
When DTSZ = 1, MAR is decremented by 2
Section 7 DMA Controller (DMAC)
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