R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 536

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Data Transfer Controller (DTC)
9.8
9.8.1
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting the module stop
state. The module stop state cannot be set while the DTC is activated. For details, refer to section
23, Power-Down Modes.
9.8.2
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0 and the corresponding MSTP bit
in RMMSTPCR must not be set to 1.
9.8.3
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
9.8.4
When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer
counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has
priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer
counter reaches 0.
9.8.5
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI and high-speed A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, if a
read/write of the relevant register is not included in the last chained data transfer, the interrupt or
activation source will be retained.
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Usage Notes
Module Stop Function Setting
On-Chip RAM
DTCE Bit Setting
DMAC Transfer End Interrupt
Chain Transfer
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010