R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 198

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
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Section 6 Bus Controller (BSC)
6.3.7
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Page 168 of 1372
Bit
15
14
13
12
11
Bit Name
BRLE
BREQOE
IDLC
ICIS1
Bus Control Register (BCR)
0
0
0
1
Initial Value
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
1: External bus release enabled
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal bus
master performs an external address space
access, or when a refresh request* is generated.
0: BREQO output disabled
1: BREQO output enabled
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle set
by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
executed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
BREQ, BACK, and BREQO pins can be used
as I/O ports
BREQO pin can be used as I/O port
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010

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