R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 919

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Note: B: Bit rate (bit/s)
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Mode
Asynchronous
Mode
Clocked Synchronous
Mode
Smart Card Interface
Mode
CKS1
0
0
1
1
SMR Setting
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
Bit Rate Register (BRR)
CKS0
0
1
0
1
ABCS
Bit
0
1
n
0
1
2
3
Bit Rate
B =
B =
B =
B =
64 × 2
32 × 2
S × 2
8 × 2
2n−1
2n+1
φ × 10
φ × 10
φ × 10
φ × 10
2n−1
2n−1
SCMR Setting
BCP2
0
0
0
0
1
1
1
1
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
6
6
6
6
Error
Error (%) = {
Error (%) = {
Error (%) = {
Section 15 Serial Communication Interface (SCI, IrDA)
BCP1
0
0
1
1
0
0
1
1
B × 64 × 2
B × 32 × 2
B × S × 2
SMR Setting
BCP0
0
1
0
1
0
1
0
1
φ × 10
φ × 10
φ × 10
2n+1
2n−1
2n−1
6
6
6
× (N + 1)
× (N + 1)
× (N + 1)
Page 889 of 1372
S
93
128
186
512
32
64
372
256
− 1 } × 100
− 1 } × 100
− 1 } × 100