R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 874

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 8-Bit Timers (TMR)
13.6
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
13.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
13.6.2
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A's for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
Page 844 of 1372
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
cleared independently.
16-bit compare match conditions.
lower 8-bit compare match conditions.
Operation with Cascaded Connection
16-Bit Counter Mode
Compare Match Count Mode
H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010