R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 337

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2426, H8S/2426R, H8S/2424 Group
6.12.3
Figure 6.96 shows the timing for transition to the bus released state.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Address bus
HWR, LWR
Data bus
BREQO
BREQ
BACK
RD
AS
φ
Transition Timing
Note: The refresh control function is not supported by the 5-V version.
[1] Low level of BREQ signal is sampled at rise of φ.
[2] Bus control signal returns to be high at end of external space access cycle.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
External space
access cycle
signal is asserted because of CBR-refreshing request, it retains low until CBR-refresh cycle starts up.
At least one state from sampling of BREQ signal.
bus release while BREQOE bit is set to 1, BREQO signal goes low.
T
Figure 6.96 Bus Released State Transition Timing
1
[1]
T
2
[2]
[3]
[4]
[5]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
[6]
Section 6 Bus Controller (BSC)
[7]
Page 307 of 1372
[8]
CPU
cycle

Related parts for R4F24268NVFQV