R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1040

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Company:
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
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Quantity:
10 000
20. Graphics Data Translation Accelerator (GDTA)
20.3.27 MC Output Frame Y Pointer Register (MCOYPR)
MCOYPR is in the MC register block and specifies the Y pointer address for an output frame.
Note: A 16-byte boundary address must be specified.
20.3.28 MC Output Frame U Pointer Register (MCOUPR)
MCOUPR is in the MC register block and specifies the U pointer address for an output frame.
Note: An 8-byte boundary address must be specified.
Rev.1.00 Jan. 10, 2008 Page 1008 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Initial value:
Initial value:
Bit
31 to 0
Bit
31 to 0
R/W:
R/W:
R/W:
R/W:
BIt:
BIt:
BIt:
BIt:
Bit Name
MC_OYPT
Bit Name
MC_OUPT
R/W
R/W
R/W
R/W
31
15
31
15
0
0
0
0
R/W
R/W
R/W
R/W
30
14
30
14
0
0
0
0
R/W
R/W
R/W
R/W
29
13
29
13
0
0
0
0
Initial
Value
All 0
Initial
Value
All 0
R/W
R/W
R/W
R/W
28
12
28
12
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
11
27
11
0
0
0
0
R/W
R/W
R/W
R/W
26
10
26
10
0
0
0
0
Description
Output Frame Y Pointer
The address should be set. 0 should be written to bits 3
to 0.
Description
Output Frame U Pointer
The address should be set. 0 should be written to bits 2
to 0.
R/W
R/W
R/W
R/W
25
25
0
9
0
0
9
0
R/W
R/W
R/W
R/W
MC_OUPT
MC_OUPT
MC_OYPT
MC_OYPT
24
24
0
8
0
0
8
0
R/W
R/W
R/W
R/W
23
23
0
7
0
0
7
0
R/W
R/W
R/W
R/W
22
22
0
6
0
0
6
0
R/W
R/W
R/W
R/W
21
21
0
5
0
0
5
0
R/W
R/W
R/W
R/W
20
20
0
4
0
0
4
0
R/W
R/W
R/W
R/W
19
19
0
3
0
0
3
0
R/W
R/W
R/W
R/W
18
18
0
2
0
0
2
0
R/W
R/W
R/W
R/W
17
17
0
1
0
0
1
0
R/W
R/W
R/W
R/W
16
16
0
0
0
0
0
0

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