R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1167
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR.
Table 22.10 shows the relationship between the number of channels in control data and bit
settings.
Table 22.10 Number of Channels in Control Data
Note: To use only one channel in control data, use channel 0.
22.4.5
Control data performs control command output to the CODEC and status input from the CODEC.
The SIOF supports the following two control data interface methods.
• Control by slot position
• Control by secondary FS
Control data is valid when data length is specified as 16 bits.
(1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot
position of control data. This method can be used in both SIOF master and slave modes. Figure
22.7 shows an example of the control data interface timing by slot position control.
Number of Channels
1
2
SIOF_SYNC
SIOF_RXD
SIOF_SCK
SIOF_TXD
Control by Slot Position (Master Mode 1 and Slave Mode 1)
Control Data Interface
Specifications:
L-channel
Slot No.0
data
Figure 22.7 Control Data Interface (Slot Position)
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Slot No.1
channel 0
Control
CD0E
1
1
R-channel
Slot No.2
data
REDG = 0
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0001,
1 frame
Slot No.3
channel 0
Control
Rev.1.00 Jan. 10, 2008 Page 1135 of 1658
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
Bit
CD1E
0
1
22. Serial I/O with FIFO (SIOF)
TDRA[3:0] = 0010,
RDRA[3:0] = 0010,
CD1A[3:0] = 0011
REJ09B0261-0100
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