R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 171

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.5.3
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation)
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor or the input of
• Overflow (O): FPSCR.Enable.O = 1 and possibility of operation result overflow
• Underflow (U): FPSCR.Enable.U = 1 and possibility of operation result underflow
• Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
Please refer section 11, Instruction Descriptions of the SH-4A Extended Functions Software
Manual about the FPU exception case in detail.
All exception events that originate in the FPU are assigned as the same exception event. The
meaning of an exception is determined by software by reading from FPSCR and interpreting the
information it contains. Also, the destination register is not changed by any FPU exception
handling operation.
If the FPU exception sources except for above are generated, the bit corresponding to source V, Z,
O, U, or I is set to 1, and a default value is generated as the operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
• Underflow (U):
• Inexact exception (I): An inexact result is generated.
FSRRA is zero
result
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value, or
zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
FPU Exception Handling
Rev.1.00 Jan. 10, 2008 Page 139 of 1658
6. Floating-Point Unit (FPU)
REJ09B0261-0100