R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 685

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.4.8
The PCI interface of this LSI supports subsets in the PCI bus version 2.2 and it can be connected
to a device with a PCI bus interface. The following figures show the timing in each operating
mode.
(1)
Figure 13.19 shows an example of a single-write cycle in host mode. Figure 13.20 shows an
example of a single-read cycle in host mode. Figure 13.21 shows an example of a burst-write
cycle in normal mode. Figure 13.22 is an example of a burst-read cycle in normal mode. Note that
the response speed of DEVSEL and TRDY differs according to the connected target device. In
PIO transfer, a single read/write cycle should be used. The configuration transfers can be issued
only in host mode.
Master Read/Write Cycle Timing
PCI Local Bus Basic Interface
PCICLK
AD[31:0]
PAR
C/BE[3:0]
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK
IDSEL
REQ
GNT
Legend:
Addr: PCI space address
Dn:
Figure 13.19 Master Write Cycle in Host Mode (Single)
nth data
DPn: nth data parity
AP: Address parity
Addr
Com
D0
AP
BE0
Rev.1.00 Jan. 10, 2008 Page 653 of 1658
DP0
Com: Command
BEn: nth data byte enable
13. PCI Controller (PCIC)
REJ09B0261-0100