R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 803

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.4.2
1. Set the WDTCNT overflow time in WDTST.
2. Set the WT/IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit.
3. When the TME bit in WDTCSR is set to 1, the WDT counter starts.
4. In watchdog timer mode, clear the WDTCNT or WDTBCNT periodically so that WDTCNT
5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and
16.4.3
In interval timer mode, the WDT generates an interval timer interrupt each time the counter
overflows. This allows interrupt generation at regular intervals.
1. Set the WDTCNT overflow time in WDTST.
2. Clear the WT/IT bit in WDTCSR to 0.
3. When the TME bit in WDTCSR is set to 1, the WDT counter starts.
4. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, generating an
does not overflow. See section 16.4.5, Clearing WDT Counters, for how to clear the WDT
counter.
generates a reset of the type specified by the RSTS bit. After the reset state is exited,
WDTCNT and WDTBCNT start counting again.
interval timer interrupt (ITI) request. WDTCNT and WDTBCNT continue counting.
Using Watchdog Timer Mode
Using Interval Timer Mode
Rev.1.00 Jan. 10, 2008 Page 771 of 1658
16. Watchdog Timer and Reset (WDT)
REJ09B0261-0100