R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1157

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame.
Initial value:
Bit
15
14 to 12 ⎯
11 to 8
7
6 to 4
3 to 0
R/W:
BIt:
Bit Name
RDLE
RDLA[3:0]
RDRE
⎯
RDRA[3:0]
RDLE
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
0
All 0
0000
0
All 0
0000
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R
R/W
11
0
R/W
RDLA[3:0]
10
0
Description
0: Disables left-channel data reception
1: Enables left-channel data reception
These bits specify the position of left-channel data in a
receive frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Receive Right-Channel Data Assigns 3 to 0
These bits specify the position of right-channel data in a
receive frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Receive Left-Channel Data Enable
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Left-Channel Data Assigns 3 to 0
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
9
0
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
R/W
8
0
RDRE
R/W
7
0
Rev.1.00 Jan. 10, 2008 Page 1125 of 1658
—
R
6
0
—
R
5
0
22. Serial I/O with FIFO (SIOF)
—
R
4
0
R/W
3
0
REJ09B0261-0100
RDRA[3:0]
R/W
2
0
R/W
1
0
R/W
0
0