R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1260

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
• The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer
• The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the
• Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a command timeout error (CTERI)
• Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a data timeout error (DTERI) occurs
Note: In a write to the card by stream transfer, the MMCIF continues data transfer to the card
Rev.1.00 Jan. 10, 2008 Page 1228 of 1658
REJ09B0261-0100
end interrupt (DTI), data response interrupt (DRPI), or pre-defined multiple block transfer end
(BTI).
end of the data busy state is detected by the data busy end interrupt (DBSYI).
occurs in the command response reception.
in the write data transmission.
even after a FIFO empty interrupt is detected. In this case, complete the command
sequence after at least 24 transfer clock cycles.