R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 13

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.1.1
Register Descriptions ......................................................................................................... 152
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 164
7.3.1
7.3.2
7.3.3
TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 170
7.4.1
7.4.2
7.4.3
MMU Functions................................................................................................................. 177
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
MMU Exceptions............................................................................................................... 182
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
Memory-Mapped TLB Configuration................................................................................ 190
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
32-Bit Address Extended Mode ......................................................................................... 199
Address Spaces ................................................................................................... 146
Page Table Entry High Register (PTEH)............................................................ 153
Page Table Entry Low Register (PTEL) ............................................................. 154
Translation Table Base Register (TTB) .............................................................. 155
TLB Exception Address Register (TEA) ............................................................ 156
MMU Control Register (MMUCR) .................................................................... 156
Page Table Entry Assistance Register (PTEA)................................................... 159
Physical Address Space Control Register (PASCR)........................................... 160
Instruction Re-Fetch Inhibit Control Register (IRMCR) .................................... 162
Unified TLB (UTLB) Configuration .................................................................. 164
Instruction TLB (ITLB) Configuration............................................................... 167
Address Translation Method............................................................................... 167
Unified TLB (UTLB) Configuration .................................................................. 170
Instruction TLB (ITLB) Configuration............................................................... 173
Address Translation Method............................................................................... 174
MMU Hardware Management............................................................................ 177
MMU Software Management ............................................................................. 177
MMU Instruction (LDTLB)................................................................................ 178
Hardware ITLB Miss Handling .......................................................................... 180
Avoiding Synonym Problems ............................................................................. 181
Instruction TLB Multiple Hit Exception............................................................. 182
Instruction TLB Miss Exception......................................................................... 183
Instruction TLB Protection Violation Exception ................................................ 184
Data TLB Multiple Hit Exception ...................................................................... 185
Data TLB Miss Exception .................................................................................. 185
Data TLB Protection Violation Exception.......................................................... 187
Initial Page Write Exception............................................................................... 188
ITLB Address Array ........................................................................................... 191
ITLB Data Array (TLB Compatible Mode)........................................................ 192
ITLB Data Array (TLB Extended Mode) ........................................................... 193
UTLB Address Array.......................................................................................... 195
UTLB Data Array (TLB Compatible Mode) ...................................................... 196
UTLB Data Array (TLB Extended Mode).......................................................... 197
Rev.1.00 Jan. 10, 2008 Page xi of xxx
REJ09B0261-0100