R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 126

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5. Exception Handling
Rev.1.00 Jan. 10, 2008 Page 94 of 1658
REJ09B0261-0100
Bit
31 to 5
4
3, 2
1
0
Bit Name
⎯
MMCAW
⎯
BRDSSLP
RTEDS
Initial
Value
All 0
1
All 0
1
1
R/W
R
R/W
R
R/W
R/W
Description
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Memory-Mapped Cache Associative Write
0: Memory-mapped cache associative write is disabled.
1: Memory-mapped cache associative write is enabled.
For further details, refer to section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Delay Slot SLEEP Instruction
0: The SLEEP instruction in the delay slot is disabled.
1: The SLEEP instruction in the delay slot is enabled.
RTE Delay Slot
0: An instruction other than the NOP instruction in the
1: An instruction other than the NOP instruction in the
(A data address error exception will occur.)
(The SLEEP instruction is taken as a slot illegal
instruction.)
delay slot of the RTE instruction is disabled. (An
instruction other than the NOP instruction is taken as
a slot illegal instruction).
delay slot of the RTE instruction is enabled.