R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1518

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29. User Break Controller (UBC)
6. When conditions have been satisfied simultaneously and independently for channels 0 and 1,
7. It is not allowed to set the pre-instruction-execution break or the operand break in the delayed
8. If the re-execution type exception and the post-instruction-execution break are in conflict for
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REJ09B0261-0100
⎯ If the post-instruction-execution break and data access break have occurred simultaneously
⎯ If the post-instruction-execution break or operand access break has occurred
resulting in identical SPC values for both of the breaks, the user break occurs only once.
However, the condition match flags are set for both channels. For example,
Instruction at address 110 (post-instruction-execution break for instruction fetch for channel 0)
→ SPC = 112, CCMFR.MF0 = 1
Instruction at address 112 (pre-instruction-execution break for instruction fetch for channel 1)
→ SPC = 112, CCMFR.MF1 = 1
slot instruction of the RTE instruction. And if the data value is included in the match
conditions of the operand break, do not set the break for the preceding the RTE instruction by
one to six instructions.
the instruction requiring two or more execution states, then the re-execution type exception
occurs. Here, the CCMFR.MF0 (or CCMFR.MF1) bit may or may not be set to 1 when the
break conditions have been satisfied.
with the re-execution type exception (including the pre-instruction-execution break) having
a higher priority, only the re-execution type exception is accepted, and no condition match
flags are set. When the exception handling has finished thus clearing the exception source,
and when the same instruction has been executed again, the break occurs setting the
corresponding flag.
simultaneously with the completion-type exception (TRAPA) having a higher priority, then
no user break occurs; however, the condition match flag is set.