R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 16

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.4 Interrupt Sources................................................................................................................ 324
10.5 Operation ........................................................................................................................... 337
10.6 Interrupt Response Time.................................................................................................... 340
10.7 Usage Notes ....................................................................................................................... 343
Section 11 Local Bus State Controller (LBSC)
11.1 Features.............................................................................................................................. 347
11.2 Input/Output Pins............................................................................................................... 350
11.3 Overview of Areas ............................................................................................................. 354
11.4 Register Descriptions......................................................................................................... 362
11.5 Operation ........................................................................................................................... 387
Rev.1.00 Jan. 10, 2008 Page xiv of xxx
REJ09B0261-0100
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.5.1
10.5.2
10.5.3
10.7.1
10.7.2
10.7.3
11.3.1
11.3.2
11.3.3
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
NMI Interrupts.................................................................................................... 324
IRQ Interrupts..................................................................................................... 324
IRL Interrupts ..................................................................................................... 325
On-Chip Peripheral Module Interrupts ............................................................... 327
Priority of On-Chip Peripheral Module Interrupts.............................................. 328
Interrupt Exception Handling and Priority ......................................................... 329
Interrupt Sequence .............................................................................................. 337
Multiple Interrupts .............................................................................................. 339
Interrupt Masking by MAI Bit............................................................................ 339
Example of Handing Routine of IRL Interrupts and Level Detection
IRQ Interrupts when ICR0.LVLMODE = 0 ....................................................... 343
Notes on Setting IRQ/IRL[7:0] Pin Function ..................................................... 344
Clearing IRQ and IRL Interrupt Requests .......................................................... 345
Space Divisions .................................................................................................. 354
Memory Bus Width ............................................................................................ 357
PCMCIA Support ............................................................................................... 358
Memory Address Map Select Register (MMSELR)........................................... 364
Bus Control Register (BCR) ............................................................................... 367
CSn Bus Control Register (CSnBCR) ................................................................ 371
CSn Wait Control Register (CSnWCR).............................................................. 377
CSn PCMCIA Control Register (CSnPCR)........................................................ 382
Endian/Access Size and Data Alignment ........................................................... 387
Areas................................................................................................................... 398
SRAM interface .................................................................................................. 403
Burst ROM Interface .......................................................................................... 412
PCMCIA Interface.............................................................................................. 416
MPX Interface .................................................................................................... 427
Byte Control SRAM Interface ............................................................................ 441
Wait Cycles between Access Cycles .................................................................. 446
........................................................... 347