R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1176

• Manufacturer Part Number: R8A77850ADBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
22.4.8
The SIOF has one type of interrupt.
(1)
Interrupts can be issued by several sources. Each source is shown as an SIOF status in SISTR.
Table 22.14 lists the SIOF interrupt sources.
Table 22.14 SIOF Interrupt Sources
Whether an interrupt is issued or not as the result of an interrupt source is determined by the
SIIER settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an
SIOF interrupt is issued.
Rev.1.00 Jan. 10, 2008 Page 1144 of 1658
REJ09B0261-0100
No. Classification
1
2
3
4
5
6
7
8
9
10
11
12
Interrupt Sources
Transmission
Reception
Control
Error
Interrupts
Bit Name Function Name
TDREQ
TFEMP
RDREQ
RFFUL
TCRDY
RCRDY
TFOVF
RFOVF
RFUDF
FSERR
SAERR
TFUDF
Transmit FIFO overflow Write to the transmit FIFO is performed
Receive FIFO overflow Serial data is received while the receive
Transmit FIFO transfer
request
Transmit FIFO empty
Receive FIFO transfer
request
Receive FIFO full
Transmit control data
ready
Receive control data
ready
Transmit FIFO
underflow
Receive FIFO
underflow
Frame Synchronous
Error
Slot assign error
Description
The transmit FIFO stores data of
specified size or more.
The transmit FIFO is empty.
The receive FIFO stores data of
specified size or more.
The receive FIFO is full.
The transmit control register is ready to
be written to.
The receive control data register stores
valid data.
Serial data transmit timing has arrived
while the transmit FIFO is empty.
while the transmit FIFO is full.
FIFO is full.
The receive FIFO is read while the
receive FIFO is empty.
A synchronous signal is input before
the specified bit number has been
passed (in slave mode).
The same slot is specified in both serial
data and control data.