R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1143

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.3.6
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. The
setting of SIRCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
Initial value:
Initial value:
Bit
31 to 16 SIRC0[15:0]
15 to 0
R/W:
R/W:
BIt:
BIt:
Receive Control Data Register (SIRCR)
Bit Name
SIRC1[15:0]
R/W
R/W
31
15
R/W
R/W
30
14
R/W
R/W
29
13
Initial
Value
Undefined
Undefined
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R/W
R/W
26
10
Description
Control Channel 0 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 0 receive data. The position of the
control channel 0 data in the transmit or receive frame
depends on the value set the CD0A bit in SICDAR.
Control Channel 1 Receive Data
These bits store data received from the SIOF_RXD pin
as control channel 1 receive data. The position of the
control 1 channel data in the transmit or receive frame
depends on the value set in the CD1A bit in SICDAR.
R/W
R/W
25
9
These bits are valid when the CD0E bit in SICDAR
is set to 1.
These bits are valid when the CD1E bit in SICDAR
is set to 1.
SIRC0[15:0]
SIRC1[15:0]
R/W
R/W
24
8
R/W
R/W
23
7
Rev.1.00 Jan. 10, 2008 Page 1111 of 1658
R/W
R/W
22
6
R/W
R/W
21
5
22. Serial I/O with FIFO (SIOF)
R/W
R/W
20
4
R/W
R/W
19
3
REJ09B0261-0100
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0

Related parts for R8A77850ADBGV#RD0Z