AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 196

IC ARM7 MCU FLASH 256K 144-LFBGA

AT91SAM7SE256-CU

Manufacturer Part Number
AT91SAM7SE256-CU
Description
IC ARM7 MCU FLASH 256K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7SE256-CU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7SE256-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7SE256-CU
Manufacturer:
ATMEL
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Part Number:
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Atmel
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22.7.1
Name:
Access:
Reset Value:
• NWS: Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
Note:
Note:
• WSEN: Wait State Enable
0: Wait states are disabled.
1: Wait states are enabled.
• TDF: Data Float Time
The external bus is marked occupied and cannot be used by another chip select during TDF cycles. Up to 15 cycles can be
defined and represents the time allowed for the data output to go to high impedance after the memory is disabled.
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
0: Chip select line is connected to two 8-bit wide devices.
1: Chip select line is connected to a 16-bit wide device.
196
Number of Wait States
WSEN
DRP
31
23
15
7
When WSEN is 0, NWS will be read to 0 whichever the previous programmed value should be.
1. Assuming WSEN Field = 0.
X + 1
SAM7SE512/256/32 Preliminary
SMC Chip Select Registers
0
1
2
(1)
30
22
14
SMC_CSR0..SMC_CSR7
Read/Write
See
6
Table 22-4 on page 195
DBW
Up to X = 127
NWS Field
Don’t Care
RWHOLD
0
1
29
21
13
5
Standard Read Protocol
BAT
NRD Pulse Length
28
20
12
4
X + 1+ ½ cycles
1 + ½ cycles
2 + ½ cycles
½ cycle
NWS
27
19
11
3
Early Read Protocol
NRD Pulse Length
X + 2 cycles
2 cycles
3 cycles
1 cycle
26
18
10
2
TDF
RWSETUP
25
17
9
1
NWR Pulse Length
6222F–ATARM–14-Jan-11
ACSS
X + 1 cycle
2 cycles
½ cycle
1 cycle
24
16
8
0

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