AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 663

• Manufacturer Part Number: AT91SAM7SE256-CU
• Description: IC ARM7 MCU FLASH 256K 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7SE256-CJ; AT91SAM7SE256-CJ

6222F–ATARM–14-Jan-11
Version
6222B
Version
6222A
Comments
SSC,
UDP,
Control endpoints are not effected by the
write 1 updated in
write 0 updated in
USART, In the US_MR register, typo fixed in bit field description
and DIV value given in bit field description
Section 33.5.1 “I/O Lines” on page
In the US_CSR register the bit field description
been updated
Comments
First issue: Preliminary
Table 38-2, “USB Communication
Section 35.6.6.1 “Compare Functions” on page
“RX_DATA_BK0: Receive Data Bank
“TXPKTRDY: Transmit Packet
392, 3rd paragraph updated.
Flow”, Supported end point size updated for transfer interrupt
“EPEDS: Endpoint Enable
“USCLKS: Clock Selection” on page 421
“TXEMPTY: TXEMPTY Interrupt Enable” on page 424
Ready”bit field in USB_CSR register.
474, updated
0”bit field in USB_CSR register.
SAM7SE512/256/32 Preliminary
“CLKO: Clock Output Select” on page 422
Disable”bit field in the USB_CSR register.
has
Change
Request
Ref.
review
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