AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 199

• Manufacturer Part Number: AT91SAM7SE256-CU
• Description: IC ARM7 MCU FLASH 256K 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7SE256-CJ; AT91SAM7SE256-CJ

23. SDRAM Controller (SDRAMC)
23.1
23.2
6222F–ATARM–14-Jan-11
Overview
Block Diagram
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from
2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word
(16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It does not support
byte Read/Write bursts or half-word write bursts. It keeps track of the active row in each bank,
thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data
in the other banks. So as to optimize performance, it is advisable to avoid accessing different
rows in the same bank.
The SDRAM Controller also supports Mobile SDRAM if VDDIO is set at 1.8V with the frequency
limitation as given in the product Electrical Characteristics. However, the SDRAMC does not
support the low-power extended mode register and deep power-down mode.
Figure 23-1. SDRAM Controller Block Diagram
Controller
Memory
PMC
Chip Select
SDRAMC
SDRAMC
Interrupt
MCK
SDRAMC
SAM7SE512/256/32 Preliminary
APB
User Interface
Controller
PIO
SDCK
SDCKE
SDCS
BA[1:0]
RAS
CAS
SDWE
NBS[3:0]
A[12:0]
D[31:0]
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